FPGA-Optimized Low-Power Content Addressable Memory for Energy-efficient and high-performance Search Systems

Abstract

Content-Addressable Memory (CAM) is crucial for high-speed search operations and pattern-matching applications such as networking, standard security, and edge computing systems. However, when directly translated onto Field-Programmable Gate Arrays (FPGAs), typical CAM architectures show excessive power consumption and poor resource efficiency because they are primarily intended for ASIC implementations. This study introduces a new power-aware FPGA-optimized Low-Power Content-Addressable Memory (LPCAM) architecture that is especially made for reconfigurable platforms in order to overcome these difficulties. To drastically cut down on needless switching during search operations, the suggested LPCAM makes use of adaptive match-line activation and selective evaluation techniques. The suggested method minimizes dynamic power usage by only activating the necessary match-lines based on the input search pattern, in contrast to conventional CAM systems that evaluate all match-lines simultaneously. Because the architecture avoids ASIC specific circuit dependencies and is implemented using LUT-based CAM cells with enable-controlled comparison logic, it is ideal for FPGA fabrics. The Vivado design suite is used to implement and validate the LPCAM design on a Xilinx Zynq-7000 (ZC7020) FPGA. Additionally, the proposed architecture shows better scalability and logic consumption, which makes it appropriate for high-performance and power-constrained search applications.